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FEATURES

LTC2207/LTC2206 16-Bit, 105Msps/80Msps ADCs DESCRIPTIO
The LTC(R)2207/LTC2206 are 105Msps/80Msps, sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700MHz. The input range of the ADC can be optimized with the PGA front end. The LTC2207/LTC2206 are perfect for demanding communications applications, with AC performance that includes 78.2dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultralow jitter of 80fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include 4LSB INL, 1LSB DNL (no missing codes) over temperature. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents Pending.
Sample Rate: 105Msps/80Msps 78.2dBFS Noise Floor 100dB SFDR SFDR >82dB at 250MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer Single 3.3V Supply Power Dissipation: 900mW/725mW Optional Clock Duty Cycle Stabilizer Out-of-Range Indicator Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) 40Msps: LTC2204 (16-Bit) 25Msps: LTC2203 (16-Bit) Single-Ended Clock 10Msps: LTC2202 (16-Bit) Single-Ended Clock 48-Pin 7mm x 7mm QFN Package
APPLICATIO S

Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE
TYPICAL APPLICATIO
3.3V SENSE VCM 2.2F 1.25V COMMON MODE BIAS VOLTAGE INTERNAL ADC REFERENCE GENERATOR
OVDD
0.5V TO 3.6V 0.1F OF CLKOUT+ CLKOUT- D15 * * * D0
AIN+ ANALOG INPUT AIN-
+
S/H AMP
-
CLOCK/DUTY CYCLE CONTROL ENC+ ENC-
16-BIT PIPELINED ADC CORE
CORRECTION LOGIC AND SHIFT REGISTER
OUTPUT DRIVERS
OGND VDD GND PGA SHDN DITH MODE OE RAND 0.1F 0.1F 3.3V 0.1F
22054 TA01
AMPLITUDE (dBFS)
ADC CONTROL INPUTS
U
U
U
LTC2207: 64K Point FFT, fIN = 14.8MHz, -1dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G05
22076fa
1
LTC2207/LTC2206 ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
48 GND 47 PGA 46 RAND 45 MODE 44 OE 43 OF 42 D15 41 D14 40 D13 39 D12 38 OGND 37 OVDD SENSE 1 VCM 2 VDD 3 VDD 4 GND 5 AIN+ 6 AIN- 7 GND 8 ENC+ 9 ENC- 10 GND 11 VDD 12 49 36 OVDD 35 D11 34 D10 33 D9 32 D8 31 OGND 30 CLKOUT+ 29 CLKOUT- 28 D7 27 D6 26 D5 25 OVDD UK PACKAGE 48-LEAD (7mm x 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49) MUST BE SOLDERED TO PCB BOARD TJMAX = 150C, JA = 29C/W TOP VIEW
Supply Voltage (VDD) ................................... -0.3V to 4V Digital Output Ground Voltage (OGND)........ -0.3V to 1V Analog Input Voltage (Note 3) ......-0.3V to (VDD + 0.3V) Digital Input Voltage .....................-0.3V to (VDD + 0.3V) Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Power Dissipation............................................ 2000mW Operating Temperature Range LTC2207C/LTC2206C ............................... 0C to 70C LTC2207I/LTC2206I ............................. -40C to 85C Storage Temperature Range .................. -65C to 150C Digital Output Supply Voltage (OVDD) .......... -0.3V to 4V
ORDER PART NUMBER LTC2207CUK LTC2206CUK LTC2207IUK LTC2206IUK
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
CONVERTER CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Integral Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Transition Noise CONDITIONS Differential Analog Input (Note 5) TA = 25C Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference

VDD 13 VDD 14 GND 15 SHDN 16 DITH 17 D0 18 D1 19 D2 20 D3 21 D4 22 OGND 23 OVDD 24
UK PART MARKING* LTC2207UK LTC2206UK LTC2207UK LTC2206UK
MIN
TYP 1.2 1.5 0.3 1 10 0.2 30 15 2.8
MAX 4 4.5 1 8.5 1.5
UNITS LSB LSB LSB mV V/C %FS
ppm/C ppm/C
LSBRMS
22076fa
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LTC2207/LTC2206
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL VIN VIN, CM IIN ISENSE IMODE CIN tAP tJITTER CMRR BW-3dB PARAMETER Analog Input Range (AIN+ - AIN-) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current MODE Pin Pull-Down Current to GND Analog Input Capacitance Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth CONDITIONS 3.135V VDD 3.465V Differential Input (Note 7) 0V AIN+, AIN- VDD (Note 10) 0V SENSE VDD (Note 11) Sample Mode ENC+ < ENC- Hold Mode ENC+ > ENC- MIN

ANALOG INPUT
1 -1 -3
TYP 1.5 to 2.25 1.25
MAX 1.5 1 3
10 6.7 1.8 1 80
UNITS VP-P V A A A pF pF ns fs RMS dB MHz
1V < (AIN+ = AIN-) <1.5V RS 25
80 700
DYNAMIC ACCURACY
SYMBOL PARAMETER SNR Signal-to-Noise Ratio
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1), 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 73.8 73.4
MIN
LTC2206 TYP 77.9 75.5
MAX
MIN
LTC2207 TYP 77.9 75.5
MAX
UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
76.5 76.2
77.8 77.5 75.4 77.5 75.3 76.7 74.8 74.5 76.2 75.4 100 100
76.5 76.2
77.8 77.5 75.4 77.5 75.3
73.8 73.4
76.7 74.8 74.5 76.2 75.4 100 100
SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic
5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0), 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1), 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 84 83
87 86
95 95 100 90 95 85 90 89 82 86
88 87
95 95 100 90 95
84 83
85 90 89 82 86
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LTC2207/LTC2206 DYNAMIC ACCURACY
SYMBOL PARAMETER SFDR Spurious Free Dynamic Range 4th Harmonic or Higher
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS unless otherwise noted. (Note 4)
CONDITIONS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (2.25V Range, PGA = 0 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 73.6 73.2

MIN
LTC2206 TYP 100 100
MAX
MIN
LTC2207 TYP 100 100
MAX
UNITS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
90
100 100 100 100
90
100 100 100 100
88
95 100 90 95 77.9 75.5
88
95 100 90 95 77.9 75.5
76.3 75.9
77.8 77.4 75.4 77.1 75.2 75.6 74.6 74.3 74.4 73.9 105 105 105 105 105 105 100 100 100 100 115 115
76.3 75.9
77.8 77.4 75.4 77.1 75.2
73.6 73.2
75.6 74.6 74.3 74.4 73.9 105 105 105 105 105 105 100 100 100 100 115 115
SFDR
Spurious Free Dynamic Range at -25dBFS Dither "OFF"
5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free Dynamic Range at -25dBFS Dither "ON"
5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)
100
115 115 115 115 110 110 105 105
100
115 115 115 115 110 110 105 105
22076fa
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LTC2207/LTC2206 COMMON MODE BIAS CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 3.135V VDD 3.465V -1mA | IOUT | 1mA
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN 1.15 TYP 1.25 40 1 2 MAX 1.35 UNITS V
ppm/C
mV/ V
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC-) VID Differential Input Voltage VICM Common Mode Input Voltage RIN Input Resistance CIN Input Capacitance LOGIC INPUTS (DITH, PGA, SHDN, RAND) VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current CIN Input Capacitance LOGIC OUTPUTS OVDD = 3.3V VOH High Level Output Voltage VOL ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL Low Level Output Voltage Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage CONDITIONS (Note 7) Internally Set Externally Set (Note 7) (See Figure 2) (Note 7) VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN
TYP
MAX
UNITS V V
0.2 1.6 1.4 6 3 3.0
k pF V V A pF

2 0.8 10 1.5
VDD = 3.3V VDD = 3.3V VOUT = 0V VOUT = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V
IO = -10A IO = -200A IO = 160A IO = 1.6mA

3.1
3.299 3.29 0.01 0.10 -50 50 2.49 0.1 1.79 0.1
0.4
V V V V mA mA V V V V
IO = -200A IO = 1.60mA IO = -200A IO = 1.60mA
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
SYMBOL PARAMETER VDD PSHDN OVDD IVDD PDIS Analog Supply Voltage Shutdown Power Output Supply Voltage Analog Supply Current Power Dissipation DC Input DC Input SHDN = VDD

POWER REQUIREMENTS
CONDITIONS
MIN 3.135 0.5
LTC2206 TYP 3.3 0.2
MAX 3.465 3.6
MIN 3.135 0.5
LTC2207 TYP 3.3 0.2
MAX 3.465 3.6
UNITS V mW V mA mW
22076fa
220 725
265 875
273 900
325 1,073
5
LTC2207/LTC2206 TIMING CHARACTERISTICS
SYMBOL PARAMETER fS tL tH tAP tD tC tSKEW tOE Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 105MHz (LTC2207), 80MHz (LTC2206) differential ENC+/ENC- = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a Sampling Frequency ENC Low Time ENC High Time Sample-and-Hold Aperture Delay ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew DATA Access time Bus Relinquish time (Note 7) (Note 7) (tC-tD) (Note 7) CL = 5pF (Note 7) (Note 7)

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 9) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7)

MIN 1 5.94 4.06 5.94 4.06
LTC2206 TYP 6.25 6.25 6.25 6.25 -0.7
MAX 80 500 500 500 500
MIN 1 4.52 3.10 4.52 3.10
LTC2207 TYP 4.762 4.762 4.762 4.762 -0.7
MAX 105 500 500 500 500
UNITS MHz ns ns ns ns ns
1.3 1.3 -0.6
2.7 2.7 0 5 5 7
4 4 0.6 15 15
1.3 1.3 -0.6
2.7 2.7 0 5 5 7
4 4 0.6 15 15
ns ns ns ns ns Cycles
"best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3.3V, fSAMPLE = 105MHz (LTC2207) or 80MHz (LTC2206), input range = 2.25VP-P with differential drive. Note 9: Recommended operating conditions. Note 10: The dynamic current of the switched capacitors analog inputs can be large compared to the leakage current and will vary with the sample rate. Note 11: Leakage current will have higher transient current at power up. Keep drive resistance at or below 1Kohm.
TIMING DIAGRAM
tAP ANALOG INPUT N+1 N+3 N+4 N+2 tH tL ENC- ENC+ tD D0-D15, OF tC N-7 N-6 N-5 N-4 N-3
N
CLKOUT+ CLKOUT -
22076 TD01
22076fa
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LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2207: INL, 105Msps
2.0 1.5 1.0 INL ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 8192 16384 24576 32768 40960 49152 57344 65536 OUTPUT CODE
22076 G01
LTC2207: DNL, 105Msps
1.0 0.8 0.6 INL ERROR (LSB) 0.4 COUNT 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 8192 16384 2457632768 40960 49152 57344 65536 OUTPUT CODE
22076 G02
LTC2207: AC Grounded Input Histogram, 105Msps
10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 32801 32803 32805 32807 32809 32811 32813 32815 32821 32817 32819 32823 50
22076 G06
0
OUTPUT CODE
22076 G03
LTC2207: 128K Point FFT, fIN = 4.93MHz, -1dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K Point FFT, fIN = 14.8MHz, -1dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K Point FFT, fIN = 14.8MHz, -10dBFS, PGA = 0, 105Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G04
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G05
AMPLITUDE (dBFS)
0
10
30 40 20 FREQUENCY (MHz)
LTC2207: SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "Off", 105Msps
140 120 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 100 80 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 140 120
LTC2207: SFDR vs Input Level, fIN = 15MHz, PGA = 0, Dither "On", 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K Point 2-Tone FFT, fIN = 14.8MHz and 18.6MHz, -7dBFS, PGA = 0, 105Msps
80 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
0
AMPLITUDE (dBFS)
100
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G09
22076 G07
22076 G08
22076fa
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LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2207: 64K Point 2-Tone FFT, fIN = 14.8MHz and 18.6MHz, -15dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K FFT, fIN = 70.1MHz, -1dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K Point FFT, fIN = 70.1MHz, -1dBFS, PGA = 1, 105Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G10
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G11
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G12
LTC2207: 128K Point FFT, fIN = 70.1MHz, -20dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 128K Point FFT, fIN = 70.1MHz, -20dBFS, PGA = 0, Dither "On", 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K Point FFT, fIN = 140.2MHz, -1dBFS, PGA = 1, 105Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G13
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G14
AMPLITUDE (dBFS)
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G15
LTC2207: SFDR vs Input Level, fIN = 140MHz, PGA = 1, Dither "Off", 105Msps
140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -70
LTC2207: SFDR vs Input Level, fIN = 140MHz, PGA = 1, Dither "On", 105Msps
140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -70 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2207: 64K Point FFT, fIN = 170.2MHz, -1dBFS, PGA = 0, 105Msps
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
-60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
0
10
30 40 20 FREQUENCY (MHz)
50
22076 G18
22076 G16
22076 G17
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LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2207: 64K Point FFT, fIN = 250.2MHz, -1dBFS, PGA = 0, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 105 100 95 SNR (dBFS) SFDR (dBc) 90 85 PGA = 0 80 75 70 0 10 30 40 20 FREQUENCY (MHz) 50
22076 G19
LTC2207: SFDR (HD2 and HD3) vs Input Frequency, 105Msps
78 77 76 75 74 73 72 71 0 100 400 300 INPUT FREQUENCY (MHz) 200 500
22076 G20
LTC2207: SNR vs Input Frequency, 105Msps
AMPLITUDE (dBFS)
PGA = 0 PGA = 1
PGA = 1
65
70
0
100
200 400 300 INPUT FREQUENCY (MHz)
500
22076 G21
LTC2207: 5MHz SNR and SFDR vs Sample Rate, 105Msps
105 100 SNR AND SFDR (dBFS) 95 90 LIMIT 85 80 75 70 0 25 75 100 125 50 SAMPLE RATE (Msps) 150 175 SNR SNR AND SFDR (dBFS) SFDR 110 105 100 95 90
LTC2207: SNR and SFDR vs Supply Voltage (VDD), fIN = 5MHz, 105Msps
UPPER LIMIT
SFDR
LOWER LIMIT 85 80 75 70 2.8 3.2 3 SUPPLY VOLTAGE (V) 3.4
22076 G23
SNR
22076 G22
LTC2207: SNR and SFDR vs Duty Cycle, 105Msps
110 300 290 100 SFDR AND SNR (dBFS) 280 270 IVDD (mA) SNR DCS OFF SNR DCS ON SFDR DCS OFF SFDR DCS ON 30 40 50 DUTY CYCLE (%)
22076 G24
LTC2207: IVDD vs Sample Rate, 5MHz Sine Wave, -1dBFS, 105Msps
90
260 250 240 230
80
70
220 210 200 0 100 50 SAMPLE RATE (Msps) 150
22076 G25
60
60
70
22076fa
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LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2206: INL, 80Msps
2.0 1.5 1.0 INL ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 8192 16384 24576 32768 40960 49152 57344 65536 OUTPUT CODE
22076 G26
LTC2206: DNL, 80Msps
1.0 0.8 0.6 INL ERROR (LSB) 0.4 COUNT 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 8192 16384 2457632768 40960 49152 57344 65536 OUTPUT CODE
22076 G27
LTC2206: 64K Point AC Grounded Histogram, 80Msps
10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 32811 32813 32815 32817 32819 32821 32823 32825 32831 35 32827 32829 32833 40 0 0
OUTPUT CODE
22076 G28
LTC2206: 128K Point FFT, fIN = 4.93MHz, -1dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point FFT, fIN = 10.1MHz, -1dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 128K Point FFT, fIN = 10.1MHz, -20dBFS, PGA = 0, Dither "Off", 80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
22076 G29
22076 G30
22076 G31
LTC2206: 128K Point FFT, fIN = 10.1MHz, -20dBFS, PGA = 0, Dither "On", 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point FFT, fIN = 15.1MHz, -1dBFS, PGA = 0, 80Msps
120 100 SFDR (dBc AND DBFS) 80 60 40 20
LTC2206: SFDR vs Input Level, fIN = 15MHz, PGA = 0, 80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
0 -70 -60
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
22076 G32
22076 G33
22076 G34
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LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2206: SFDR vs Input Level fIN = 15MHz, PGA = 0, Dither "On", 80Msps
140 120 SFDR (dBc AND DBFS) AMPLITUDE (dBFS) 100 80 60 40 20 0 -70 -60 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point 2-Tone FFT, fIN = 14.8MHz and 18.6MHz, -7dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point 2-Tone FFT, fIN = 14.8MHz and 18.6MHz, -15dBFS, PGA = 0, 80Msps
-50 -40 -30 -20 INPUT LEVEL (dBFS)
-10
0
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
22076 G35
22076 G36
22076 G37
LTC2206: 64K Point FFT, fIN = 25.1MHz, -1dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point FFT, fIN = 70.2MHz, -1dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point FFT, fIN = 70.2MHz, -1dBFS, PGA = 1, 80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
22076 G38
22076 G39
22076 G40
LTC2206: 64K Point 2-Tone FFT, fIN = 69.2MHz and 76.5MHz, -7dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point 2-Tone FFT, fIN = 69.2MHz and 76.5MHz, -15dBFS, PGA = 0, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point FFT, fIN = 140.2MHz, -1dBFS, PGA = 0, 80Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30 FREQUENCY (MHz)
AMPLITUDE (dBFS)
35
40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
22076 G41
22076 G42
22076 G43
22076fa
11
LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2206: SFDR vs Input Level, fIN = 140.2MHz, PGA = 0, Dither "Off", 80Msps
130 120 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 SFDR (dBc AND dBFS) 130 120 110 AMPLITUDE (dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0
LTC2206: SFDR vs Input Level, fIN = 140.2MHz, PGA = 0, Dither "On", 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2206: 64K Point FFT, fIN = 170.2MHz, -1dBFS, PGA = 1, 80Msps
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
22076 G44
22076 G45
22076 G46
LTC2206: 64K Point FFT, fIN = 250.2MHz, -1dBFS, PGA = 1, 80Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 105 100 95 90
LTC2206: SFDR (HD2 and HD3) vs Input Frequency, 80Msps
79 78 77 76 SNR (dBFS) 75 74 73 72 71 70 69 0 400 100 300 200 INPUT FREQUENCY (MHz) 500
LTC2206: SNR vs Input Frequency, 80Msps
AMPLITUDE (dBFS)
SFDR (dBc)
85 PGA = 1 80 PGA = 0 75 70 65
PGA = 0 PGA = 1
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
60
0
100 300 400 200 INPUT FREQUENCY (MHz)
500
22076 G49
22076 G47
22076 G48
LTC2206: 5MHz SFDR and SNR vs Sample Rate, 80Msps
105 SFDR 100 SFDR AND SNR (dBRS) 95 90 LIMIT 85 80 75 70 0 20 40 100 120 140 160 SAMPLE RATE (MHz)
22076 G50
LTC2206: SNR and SFDR vs Supply Voltage (VDD), fIN = 5MHz, 80Msps
110 LOWER LIMIT 105 SNR AND SFDR (dBFS) 100 SFDR IVDD (mA) SNR UPPER LIMIT 95 90 85 80 75 250 240 230 220 210 200 190 180 170 160 150 3.2 3 SUPPLY VOLTAGE (V) 3.4
22076 G51
LTC2206: IVDD vs Sample Rate, 5MHz Sine Wave, -1dBFS, 80Msps
SNR
60
80
70 2.8
0
20
60 80 40 SAMPLE RATE (Msps)
100
22076 G52
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LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS
Offset Voltage vs Temperature, Internal Reference, 5 Units
8 6 OFFSET VOLTAGE (mV) 4 2 0 -2 -4 -6 -8 -40 -15 10 35 TEMPERATURE (C) 60 85
22076 G53
Normalized Full-Scale Error vs Temperature, Internal Reference, 5 Units
1.001 1.000 NORMALIZED FULL-SCALE 0.999 0.998 0.997 0.996 0.995 -40 110 105 100 95 SFDR (dBFS) 90 85 80 75 70 65 60 -15 10 35 TEMPERATURE (C) 60 85
22076 G54
SFDR vs Analog Input Common Mode Voltage, 10MHz and 70MHz, -1dBFS, PGA = 0
10MHz
70MHz
1.75 0.75 1.25 1.5 0.5 2 1 ANALOG INPUT COMMON MODE VOLTAGE (V)
22076 G55
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LTC2207/LTC2206 PIN FUNCTIONS
SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2F. Ceramic chip capacitors are recommended. VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pins 5, 8, 11, 15, 48, 49): ADC Power Ground. AIN+ (Pin 6): Positive Differential Analog Input. AIN- (Pin 7): Negative Differential Analog Input. ENC+ (Pin 9): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. ENC- (Pin 10): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC-. Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1F capacitor for a single-ended Encode signal. SHDN (Pin 16): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 17): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital Outputs. D15 is the MSB. OGND (Pins 23, 31 and 38): Output Driver Ground. OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1F capacitor. CLKOUT- (Pin 29): Data Valid Output. CLKOUT- will toggle at the sample rate. Latch the data on the falling edge of CLKOUT-. CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+ will toggle at the sample rate. Latch the data on the rising edge of CLKOUT+. OF (Pin 43): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred. OE (Pin 44): Output Enable Pin. Low enables the digital output drivers. High puts digital outputs in Hi-Z state. MODE (Pin 45): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 46): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interferance. PGA (Pin 47): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.25VP-P. High selects a front-end gain of 1.5, input range of 1.5VP-P. GND (Exposed Pad, Pin 49): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground.
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LTC2207/LTC2206 BLOCK DIAGRAM
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND VDD
AIN-
DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER
RANGE SELECT SENSE PGA VCM ADC REFERENCE
ADC CLOCKS OVDD CLKOUT+ CLKOUT- OF CONTROL LOGIC OUTPUT DRIVERS D15 D14 D1 D0
BUFFER VOLTAGE REFERENCE
DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER
* * *
OGND ENC+ ENC- SHDN PGA RAND MODE DITH OE
22076 F01
Figure 1. Functional Block Diagram
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LTC2207/LTC2206 OPERATION
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = -20Log ((V22 + V32 + V42 + ... VN2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3nd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC- voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from convertion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER)
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LTC2207/LTC2206 APPLICATIONS INFORMATION
CONVERTER OPERATION The LTC2207/LTC2206 are CMOS pipelined multistep converters with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles clock later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2207/LTC2206 have two phases of operation, determined by the state of the differential ENC+/ENC- input pins. For brevity, the text will refer to ENC+ greater than ENC- as ENC high and ENC+ less than ENC- as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer.
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LTC2207/LTC2206 APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2207/ LTC2206 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transitors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing 0.5625V for the 2.25V range (PGA = 0) or 0.375V for the 1.5V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 2) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2F or greater. Input Drive Impedence As with all high performance, high speed ADCs the dynamic performance of the LTC2207/LTC2206 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample-and-hold circuit will connect the 4.9pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recomended to have a source impedence of 100 or less for each input. The source impedence should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.
LTC2207/LTC2206 VDD
CSAMPLE 4.9pF CPARASITIC 1.8pF CSAMPLE 4.9pF CPARASITIC 1.8pF VDD
AIN+ VDD
AIN-
1.6V 6k ENC+ ENC- 6k 1.6V
22076 F02
Figure 2. Equivalent Input Circuit
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18
LTC2207/LTC2206 APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS Input Filtering A first order RC lowpass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC2207/LTC2206 have a very broadband S/H circuit, DC to 700MHz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended RC filter. Figures 3, 4a and 4b show three examples of input RC filtering at three ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated--this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2207/ LTC2206 do not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. Transformer Coupled Circuits Figure 3 shows the LTC2207/LTC2206 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50 can reduce the input bandwidth and increase
VCM 2.2F 5 10 T1 8.2pF 35 8.2pF 0.1F 10 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F 35 5 AIN- 8.2pF
22076 F03
high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than flux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25V. Figure 4b shows the same circuit with components suitable for higher input frequencies.
VCM 2.2F 0.1F ANALOG INPUT 25 T1 1:1 25 10 10 0.1F 4.7pF 5 AIN+ 4.7pF LTC2207/ LTC2206
0.1F
5 AIN- 4.7pF
22076 F04a
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F
Figure 4a. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz
VCM 5 AIN+ 2.2F LTC2207/ LTC2206 0.1F ANALOG INPUT 25 T1 1:1 0.1F 5 2.2pF AIN+ LTC2207/ LTC2206
0.1F
25
5 2.2pF
AIN-
22076 F04b
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F
Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 150MHz
Figure 4b. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 250MHz to 500MHz
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. Reference Operation Figure 6 shows the LTC2207/LTC2206 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2207/LTC2206 have three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.25VP-P (PGA = 0). A 1.25V output VCM is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; it will not be stable without this capacitor. The minimum value required for stability is 2.2F. The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and is not accessible for external use. The SENSE pin can be driven 5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1F (or larger) ceramic capacitor. PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.25VPP; PGA = 1 selects an input range of 1.5VP-P. The 2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be 2.4dB worse. See the Typical Performance Characteristics section of this datasheet.
LTC2207/ LTC2206 TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE LTC2207/ LTC2206 VCM 25 12pF AIN-
22076 F05 22076 F06
RANGE SELECT AND GAIN CONTROL
INTERNAL ADC REFERENCE PGA
SENSE
VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT 2.2F 25 12pF AIN+
+
CM
2.5V BANDGAP REFERENCE BUFFER 1.25V
+ -
-
2.2F
AMPLIFIER = LTC6600-20, LTC1993, ETC.
Figure 5. DC Coupled Input with Differential Amplifier
Figure 6. Reference Circuit
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LTC2207/LTC2206 APPLICATIONS INFORMATION
LTC2207/ LTC2206 VDD TO INTERNAL ADC CLOCK DRIVERS 1.6V 6k ENC LTC2207/ LTC2206 ENC-
22076 F07
VDD 1.25V VCM 2.2F 2 6 SENSE 2.2F
+
3.3V 1F
LTC1461-2.5 4
VDD 1.6V 6k
22076 F08a
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
Figure 8a. Equivalent Encode Input Circuit
0.1F
T1 50
ENC+
100 8.2pF 0.1F 50
LTC2207/ LTC2206
VTHRESHOLD = 1.6V
ENC+ 1.6V ENC- LTC2207/ LTC2206
0.1F
ENC-
22076 F08b
0.1F
22076 F09
T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE
Figure 8b. Transformer Driven Encode
Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter
3.3V MC100LVELT22 3.3V Q0 D0 ENC+ ENC- LTC2207/ LTC2206
Q0
22076 F10
Figure 10. ENC Drive Using a CMOS to PECL Translator
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Driving the Encode Inputs The noise performance of the LTC2207/LTC2206 can depend on the encode signal quality as much as for the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates The maximum encode rate for the LTC2207 is 105Msps. The maximum encode rate for the LTC2206 is 80Msps. For the ADC to operate properly the encode signal should have a 50% (5%) duty cycle. Each half cycle must be at least 4.52ns for the LTC2207 internal circuitry to have enough settling time for proper operation. For the LTC2206, each half cycle must be at least 5.94ns. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2207/LTC2206 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2207/LTC2206 is 1Msps.
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LTC2207/LTC2206 APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Digital Output Buffers Table 1. MODE Pin Function
MODE 0(GND) 1/3VDD 2/3VDD VDD Output Format Offset Binary Offset Binary 2's Complement 2's Complement Clock Duty Cycle Stabilizer Off On On Off
Figure 11 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2207/LTC2206 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the output buffer has a series resistor of 33 on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format The LTC2207/LTC2206 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the MODE pin.
Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. A logic high on the OF pin indicates an overflow or underflow. Output Clock The ADC has a delayed version of the encode input available as a digital output. Both a noninverted version, CLKOUT+ and an inverted version CLKOUT- are provided. The CLKOUT+/CLKOUT- can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data can be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT-. CLKOUT+ falls and CLKOUT- rises as the data outputs are updated.
LTC2207/LTC2206 CLKOUT CLKOUT+
OF
OF
D15
D15/D0
D14
D14/D0
LTC2207/LTC2206 OVDD VDD VDD 0.5V TO 3.6V 0.1F OVDD DATA FROM LATCH PREDRIVER LOGIC 33 TYPICAL DATA OUTPUT OGND D0
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D2
* * *
D2/D0
D1
D1/D0
RAND = HIGH, SCRAMBLE ENABLED
RAND
D0
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Figure 11. Equivalent Circuit for a Digital Output Buffer
Figure 12. Functional Equivalent of Digital Output Randomizer
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is "Randomized" by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output Randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same
LTC2207/LTC2206 CLKOUT OF D15 * * * D0
1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the VDD of the ADC. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Internal Dither The LTC2207/LTC2206 are 16-bit ADCs with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 15, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off.
AIN+ ANALOG INPUT AIN- S/H AMP
16-BIT PIPELINED ADC CORE
DIGITAL SUMMATION
OUTPUT DRIVERS
CLOCK/DUTY CYCLE CONTROL
PRECISION DAC
MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR
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ENC
+
ENC
-
DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF
Figure 13. Functional Equivalent Block Diagram of Internal Dither Circuit
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LTC2207/LTC2206 APPLICATIONS INFORMATION
PC BOARD FPGA CLKOUT
OF
D15/D0 D15 LTC2207/ LTC2206 D14/D0 D14
D2/D0
* * *
D2
D1/D0 D1
D0
D0
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Figure 14. Descrambling a Scrambled Digital Output
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Grounding and Bypassing The LTC2207/LTC2206 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2207/LTC2206 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2207/LTC2206 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2207/LTC2206 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible.
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Silkscreen Top
Top Side
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Inner Layer 2
Inner Layer 3
Inner Layer 4
Inner Layer 5
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Bottom Side
Silkscreen Bottom
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LTC2207/LTC2206 APPLICATIONS INFORMATION
Ordering Guide:
DEMO BOARD NUMBER DC918C-A DC918C-B DC918C-C DC918C-D DC918C-E DC918C-F DC918C-G DC918C-H DC918C-I DC918C-J DC918C-K DC918C-L PART NUMBER LTC2207CUK LTC2207CUK LTC2206CUK LTC2206CUK LTC2205CUK LTC2205CUK LTC2204CUK LTC2207CUK-14 LTC2207CUK-14 LTC2206CUK-14 LTC2206CUK-14 LTC2205CUK-14 RESOLUTION 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 14-Bit 14-Bit 14-Bit 14-Bit 14-Bit SPEED 105Msps 105Msps 80Msps 80Msps 65Msps 65Msps 40Msps 105Msps 105Msps 80Msps 80Msps 65Msps INPUT FREQUENCY 1MHz to 70MHz 70MHz to 140MHz 1MHz to 70MHz 70MHz to 140MHz 1MHz to 70MHz 70MHz to 140MHz 1MHz to 70MHz 1MHz to 70MHz 70MHz to 140MHz 1MHz to 70MHz 70MHz to 140MHz 1MHz to 70MHz USB I/F BOARD DC718 DC718 DC718 DC718 DC718 DC718 DC718 DC718 DC718 DC718 DC718 DC718
See Web site for ordering details or contact local sales.
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LTC2207/LTC2206 PACKAGE DESCRIPTION
UK Package 48-Lead Plastic QFN (7mm x 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 0.05
5.15 0.05 6.10 0.05 7.50 0.05 (4 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 7.00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP
47 48 0.40 0.10 1 PIN 1 CHAMFER 2
PIN 1 TOP MARK (SEE NOTE 6)
5.15 0.10 (4-SIDES)
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
(UK48) QFN 1103
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2207/LTC2206 RELATED PARTS
PART NUMBER LTC1747 LTC1748 LTC1749 LTC1750 LTC1993-2 LTC1994 LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2220 LTC2220-1 LTC2224 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2284 LTC2299 LTC5512 LTC5514 LTC5515 LTC5516 LTC5517 LTC5522 DESCRIPTION 12-Bit, 80Msps ADC 14-Bit, 80Msps, 5V ADC 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps, 5V Wideband ADC High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 16-Bit, 40Msps, 3.3V ADC 16-Bit, 65Msps, 3.3V ADC 16-Bit, 80Msps, 3.3V ADC 16-Bit, 105Msps, 3.3V ADC 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 12-Bit, 170Msps ADC 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 14-Bit, 80Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain COMMENTS 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 61.6dB SNR, 5mm x 5mm QFN Package 395mW, 61.6dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 320mW, 72.5dB SNR, 5mm x 5mm QFN Package 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN 230mW, 71.6dB SNR, 5mm x 5mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450 MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
1.5 GHz to 2.5GHz Direct Conversion Quadrature High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator Demodulator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports
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32 Linear Technology Corporation
(408) 432-1900
LT 0606 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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